They seem important, causing PCI config register bits 0xed[5: Also tried many different driver revisions. Home Questions Tags Users Unanswered. Option ROM sets this to either 0xf1 or 0x The original bytes were e8 xx xx , where e8 is the opcode for the CALL instruction, and the bit immediate operand is the relative branch target. Have you ever used your external enclosure with a different computer?
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I can’t seem to hot swap an external SATA drive.
The last byte of the file is used as a checksum. Nov 7, 4. BTW i am trying to set ide mode so i simply changed the 3 instances of b1 to 91 trying to put sata interface into legacy mode and set the checksum.
Trying to do that in the option ROM causes a several-minute hang during boot when loading the option ROM again, seemingly waiting for a disk and giving upeven when a PATA disk is present. Only thing diff was the last checkmark which I gave a try but since it didn’t increase the speed I unmarked it again. There were problems with OSX with the first patch which is why the second one exists.
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I made changes at three locations: At this point in the code, register cl should contain the byte read from PCI configuration register 0xdf. The settings were already as shown above.
JMicron JMB eSATA Controller Drivers JMB36X
It seems like bits [1: The bytes b1 02 90 are two x86 instructions mov cl, 0x02; nop; See previous reply. Which can be found here: Does anyone have any other tips?
If so, I would start with the first patched ROM the one that sets df[1: Can you work that changes at latest bios ver 1. You can use these HTML tags. Log in or Sign up.
Home Questions Tags Users Unanswered. Your name or email address: Jmciron to this Esaata postthe JMicron JMB chipset supports hotplugging but the manufacturer’s drivers don’t. Sign up using Facebook.
Stephen 1 3 9. You might try looking through the Linux kernel sources to see if the driver for the 88SE gives any clues as to how the chip works…. Those three bytes used to be a function call to a function that would read a byte from the PCI configuration space register diand return the result in cl.
JMicron JMB Add-on Card AHCI mode « Blog
Those connected at boot were not detected. I want to use latest bios because it will be better 1. On many mainboards, the Jmicron controllers usually 2 onboard share a single x1 PCI-E lane with other onboard devices such as giga ethernet controllers, sound, etc.
e-SATA terribly slow with JMicron JMB363
It’s a bad bottleneck and has been found to be a serious issue. Problems Only modifying register df[1: The original bytes were e8 xx xxwhere e8 is the opcode for the CALL instruction, and the bit immediate operand is the relative branch target.
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